1. Technical Field
The present invention relates to processors configured for performing multiple operations simultaneously, more specifically to a processing architecture that minimizes processing latency by performing multiple concurrent operations, for example network address comparison in a network workgroup switch.
2. Background Art
Switched networks, such as local area networks or wide area networks, use a network switch, also referred to as a workgroup switch, for supplying data frames between network nodes via a media. Conventional switched local area network architectures use a media access control (MAC) enabling a network interface device within each network node (e.g., workstation, switch) to access the media.
The network switch is configured for switching data frames received from a transmitting node to a destination node based on the header information in the received data frame at the MAC layer, including source address and destination address. For example, the Ethernet (IEEE 802.3) protocol specifies a header, following a 64-bit preamble and start frame delimiter, having a 6-byte destination address followed by a 6-byte source address. One possible arrangement for generating a frame forwarding decision uses the destination address in a direct addressing scheme, where the network switch accesses a table storing switching data for a plurality of network addresses. For example, the switching data for a given destination address may be stored at a memory location having a table address corresponding to the destination address. Such a direct addressing arrangement, however, is not practical because the resulting memory address space is prohibitively large.
In particular, a workgroup switch having several high speed ports, for example 100 Mb/s or 1 Gb/s ports, requires frame forwarding decisions to be performed in a relatively short period of time to support wire-rate traffic, where the data packets are switched according to the data rate of the network media. For example, a network switch having twelve (12) 100 Mb/s ports and one Gb/s port requires a frame forwarding and/or filtering decision to be executed approximately within 300 nanoseconds. Since any memory access requires two clock cycles (one for addressing the memory, one for reading data from the addressed location), it becomes extremely difficult for the network switch to make frame forwarding decisions at the wire rate.
Conventional approaches to optimizing processing speed include implementing hardwired logic to execute logic operations. Hardwired logic has the advantage of executing logic operations faster than instruction-based processors. However, the hardwired logic cannot be modified or updated, absent a complete replacement of the silicon-based logic. Hence, instruction-based processing has the advantage of flexibility at the expense of processing speed.
Although conventional network switches use MAC-based switching protocols, referred to as layer-2 protocols, efforts are underway to develop layer-3 switching protocols, for example Internet protocol (IP) based addressing. Layer-3 switching protocols are still evolving, hence hardwired lookup schemes do not provide the flexibility and programmability currently required to implement layer3 switching in workgroup switches. However, instruction-based processing does not provide sufficient throughput for high-speed workgroup switches that require frame forwarding decisions to be performed on the order of 300 nanoseconds.